This invention relates to a test circuit of input architecture for Erasable and Programmable Logic Device.
The Erasable and Programmable Logic Device (hereinafter referred to as EPLD) made by the Erasable Programmable Read Only Memory(EPROM) technology has been widely used, and EPLD array architecture was disclosed in U.S. Pat. No. 4,609,986. This input architecture is a transparent latch and can form input data into flow through data or into latched data. There are two types of input architecture, one of flow through architecture, the other of user configurable logic. The input architecture of the user configurable logic is generally composed of flow through architecture, flip-flop architecture, or latch architecture. However, this architecture doesn't have a test function for testing just the input architecture of the user configurable logic.